Digital electronic systems are comprised of essentially three different types of components: memory, microprocessor, and logic components. Memory devices store information such as, for example, the contents of a spreadsheet or database. Microprocessors execute software instructions to perform a wide variety of tasks such as running a word processing program or video game. Logic devices provide specific functions, including device-to-device interfacing, data communication, signal processing, data display, timing and control operations, and almost every other function a system must perform.
Logic devices may include either fixed or programmable functions. Fixed logic devices, as the name suggests, are permanent and perform a predetermined function or set of functions. Once manufactured, these functions cannot be altered. By contrast, programmable logic devices offer a wide range of possible logic functions, which can be programmed and altered by a designer to perform desired logic functions.
There are various types of programmable logic devices, including the Programmable Logic Arrays (PLA), Programmable Array Logic (PAL), the Programmable Logic Device (PLD), and the Complex Programmable Logic Device (CPLD). Common among these programmable logic devices is some form of logical planes, i.e., array of AND, OR functional gates, that contain some mechanism for programming (and in some instances, even reprogramming) one or more desired logic functions. For example, FIG. 1 shows a basic schematic of a PLA logic block that contains an AND array and an OR array with programmability in both planes. The “Xs” indicate where connections may be made between the wires. As can be seen, three different logic operations can be attained using this basic PLA logic block.
Early programmable logic device architectures, including the technologies used to implement their programmability, were often not up to par with their application specific integrated circuit (ASIC) counterparts. In fact, not until the introduction of the CPLD did programmable logic devices achieve wide market adoption. A CPLD consists of three principal component types: logic blocks, programmable interconnects, and input/output (I/O) blocks. The programmable interconnect matrix in a CPLD is typically configured so that it is capable of connecting any input or output of a given logic block to any input or output of another logic block.
FIG. 2A is an architectural diagram of a commercially available CPLD 20 manufactured by Altera Corporation. The CPLD 20 comprises an array of blocks, referred to as Logic Array Blocks (LABs) 200, interconnect wires, referred to as a Programmable Interconnect Array (PIA) 202. The PIA 202 is capable of interconnecting any LAB input or output to any other LAB. Each LAB 200 includes a plurality of “macrocells” 204, which can be configured to perform various combinatorial or sequential logic functions. Each macrocell 204 comprises a set of programmable product terms (part of an AND-plane) that feed an OR-gate and a flip-flop. As illustrated in FIG. 2B, the number of inputs to the OR-gate in a given macrocell is variable, and may be programmed so that the CPLD performs desired combinatorial or sequential logic functions.
Another user-programmable integrated circuit that is in widespread use is the Field Programmable Gate Array (FPGA). One of the principal benefits of FPGAs over other programmable device structures (such as those discussed above) is that FPGAs support a much higher logic capacity. As shown in FIG. 3, a typical FPGA 30 comprises three types of configurable elements: configurable logic blocks 300 arranged in a two-dimensional array, input/output (I/O) blocks 302, and programmable interconnects 304. The logic blocks 300 provide the functional elements for implementing a user's design; the I/O blocks 302 provide an interface between the package pins and the internal signal lines of the integrated circuit; and the programmable interconnects 304 provide routing paths to connect the inputs and outputs of the logic blocks 300 and I/O blocks 302.
There are many architectural styles used to implement an FPGA. A key distinguishing feature among the various styles is the type of programmable switching device used to configure (i.e. program) the FPGA. The main programmable switch technologies are: antifuse, EEPROM (electrically erasable programmable read only memory) or floating gate (FG) non-volatile memory (NVM), SRAM (static random access memory), and SONOS (silicon-oxide-nitride-oxide-silicon) based NVM. Each of these technologies can be used to form a programmable switch capable of storing logic “1” and logic “0” states. The logic states of a plurality of these programmed switches determine the configuration settings of the logic blocks of the FPGA, and consequently the logic functions provided by the FPGA.
FIG. 4 is a table comparing various integration and performance characteristics of the four main programmable switch technologies. As can be seen, use of each of the technologies presents benefits as well as drawbacks. For example, while SRAM programmable switch technology is compatible with CMOS (Complementary Metal Oxide Semiconductor) technology, and may even be available in advanced 90 nm or below CMOS technologies, the anti-fuse, EEPROM/FG and SONOS NVM technologies are not. Anti-fuse, EEPROM/FG and SONOS NVM technologies require extra masking and/or special processing steps beyond that used in established CMOS processes. Anti-fuse, EEPROM/FG and SONOS NVM technologies also have a limited lifespan, since they can be reprogrammed only a finite number of times; require special charge pump circuitry to generate the high voltages needed for programming; and are difficult to scale with CMOS scaling. These drawbacks, particularly when weighed against the benefits gained by use of SRAM technology has led SRAM to become the leading programmable switch technology used in FPGAs. SRAM is compatible with existing CMOS processing technologies, may be fabricated in advanced logic fabrication processes (e.g. 90 nm or below), and can be easily scaled along with the scaling of a CMOS process. For these reasons, most commercially available FPGAs use SRAM-based programmable switching technology.
FIG. 5 is a circuit diagram of a programmable switch 50 using a conventional 6T SRAM cell. The 6T SRAM cell comprises two cross-coupled CMOS inverters (two transistors each) 500, 502 and two access transistors 504, 506. The SRAM cell 50 is coupled to the control input (i.e. gate) of an NMOS passgate 508. When a logic one is stored in the SRAM cell 50, the NMOS passgate 508 acts as a closed switch. On the other hand, when a logic zero is stored in the SRAM cell 50, the NMOS passgate 508 acts as an open switch.
6T SRAM cells are used extensively in standard FPGAs. Not only are they used to control passgates, as described in the previous paragraph, they are also used as “configuration bits” that control select lines of multiplexers which drive the logic blocks of the FPGA. FIG. 6 illustrates these two functions in a typical FPGA 60. First and second 6T SRAM cells 600 and 602 control respective passgates 604 and 606, to connect a first logic block 608 located in the upper left hand corner (represented by the AND gate) of the FPGA 60 to a second logic block 610 located in the lower right hand corner of the FPGA 60. A third 6T SRAM configuration bit 612 controls a multiplexer 614, to complete the connection between the first logic block 608 and the second logic block 610.
FIG. 7 is a drawing illustrating how 6T SRAM configuration bits are connected to and control the selection in a 4:1 multiplexer. The 4:1 multiplexer 70 is similar to that found in a typical SRAM-based FPGA. The 4:1 multiplexer has four inputs 700 (also labeled In0, In1, In2, In3) coupled to respective input buffers 702 and an output 704 (also labeled “Out0”). NMOS passgate transistors 704 are coupled between each of the four input buffers 702 and an output buffer 706. Four 6T SRAM cells 708 are coupled to the gates of NMOS passgate transistors 704. Together, the 6T SRAM cells 708 and NMOS passgate transistors 704 form 6T SRAM configuration bits, which control which of the four inputs 700 is routed to the output 704. So, for example, if the logic state of the 6T SRAM cell second from the right stores a logic “1”, and the remaining 6T SRAM cells store a logic “0”, then the input 700 that is second from the bottom (i.e. input In2) is routed to the output 704.
Another common circuit found in FPGAs is the look-up table (or “LUT”). A LUT performs a variety of Boolean logic functions based on the states and selection of a plurality of memory elements. In SRAM-based FPGAs, the memory elements are 6T SRAM cells. FIG. 8 is an architectural drawing of a logic block 80 of an SRAM-based FPGA, which illustrates the relationship between a LUT 800 and other components of the logic block 80. The four-input LUT 800 implements four input combinational logic functions. A first configuration bit 802 selects a desired logic function from the LUT 80. A multiplexer 804, which is controlled by a second configuration bit 806, is used to select either the LUT output or the output of an optional flip-flop (or “latch”) 808.
FIG. 9 is a more detailed drawing of a typical prior art SRAM-based LUT 90. A plurality of 6T SRAM memory elements is coupled to a chain of NMOS pass-gates. Select lines In1, In2, In3, In4 are coupled to the gates of the chain of NMOS pass-gates. The desired Boolean function is determined by the logic values set on select lines, In1, In2, In3, In4 and the logic values stored in the selected memory elements.
Although SRAM-based programmable switch technology has become the preferred programmable switch technology, its use does present other drawbacks. One major drawback of SRAMs is that they occupy a large percentage of the programmable fabric of an SRAM-based FPGA. A single 6T SRAM configuration bit has seven active devices, six to implement the SRAM cell and a seventh for the passgate. Hence, even a single 6T SRAM configuration bit occupies a significant amount of base silicon. This problem is compounded by the fact that present day SRAM-based FPGAs can contain ten to fifty million SRAM cells. Accordingly, SRAM-based FPGAs, although offering many benefits, have the serious drawback of the SRAM cells consuming a large portion of the FPGA chip area. As shown in FIG. 10, the SRAM cells, associated MOS passgates and error correction circuitry may consume 70% or more of the programmable blocks of the FPGA.
SRAMs are also susceptible to radiation-induced soft errors. A radiation-induced soft error occurs when neutrons or alpha particles from the environment impinge on the SRAM and cause it to change state. To prevent radiation-induced errors, special error correction circuitry is routinely included with the SRAM cells.
Finally, SRAM-based FPGAs are volatile (see FIG. 4), meaning that the SRAM-based configuration bits must be reprogrammed (i.e. reconfigured) every time the FPGA is powered down and then powered up again. To compensate for this volatility aspect, the configuration bits may be, as is currently done, programmed into a configuration memory (e.g. non-volatile memory). During boot up, the configuration memory provides the configuration bits needed to configure the desired logic functions. In addition to the drawback of having to wait for the FPGA to be configured to boot-up, large amounts of power are needed to complete the boot up process. Because the states of the various SRAMs in SRAM based FPGA are random at power-up, and there are millions of SRAMs on a typical SRAM-based FPGA, there is a chance that most of the SRAMs are in the same state at the initial stages of power-up. Under these conditions, large currents can be generated in the FPGA. To avoid such high current conditions, special power supply and control circuitry must be employed to ensure that configuration is done properly and without damaging the FPGA. The need for special power supply and control circuitry adds further complexity and cost to systems using SRAM-based FPGAs.
Given the foregoing limitations and drawbacks of prior art programmable logic structures, it would be desirable to have a programmable logic structure, for example an FPGA, that is reconfigurable, uses non-volatile memory elements, is radiation hard, and can be more densely integrated than currently available programmable logic structures.